Partial-order reduction in symbolic state space exploration-Reference-Cited by-同舟云学术

Partial-order reduction in symbolic state space exploration

Published:1997 Issue: Volume: Page:340-351
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
Short-container-title:

Author:

Alur R.,Brayton R. K.,Henzinger T. A.,Qadeer S.,Rajamani S. K.

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-63166-6_34.pdf

Reference14 articles.

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2. J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Symbolic Model Checking: 1020 States and Beyond. Information and Computation, 98:142–170, 1992.

3. R.K.Brayton,G.D.Hachtel,A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S.-T. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R.K. Ranjan, S. Sarwary, T.R. Shiple, G. Swamy, and T. Villa. VIS: A System for Verification and Synthesis. In Proc. of the 8th International Conference on Computer-Aided Verification, vol. 1102 of Lecture Notes in Computer Science, pages 428–432. Springer, 1996.

4. C.-T. Chou and D.A. Peled. Formal Verification of a Partial-Order Reduction Technique for Model Checking. In Proc. of the Second International Workshop on Tools and Algorithms for the Construction and Analysis of Systems, vol. 1055 of Lecture Notes in Computer Science, pages 241–257. Springer, 1996.

5. D.L. Dill. Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits. MIT Press, 1989.

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