VIS: A system for verification and synthesis-Reference-Cited by-同舟云学术

VIS: A system for verification and synthesis

Published:1996 Issue: Volume: Page:428-432
ISSN:0302-9743
Container-title:Computer Aided Verification
language:
Short-container-title:

Author:

Brayton Robert K.,Hachtel Gary D.,Sangiovanni-Vincentelli Alberto,Somenzi Fabio,Aziz Adnan,Cheng Szu -Tsung,Edwards Stephen,Khatri Sunil,Kukimoto Yuji,Pardo Abelardo,Qadeer Shaz,Ranjan Rajeev K.,Sarwary Shaker,Staple Thomas R.,Swamy Gitanjali,Villa Tiziano

Publisher

Springer Berlin Heidelberg

Link

http://link.springer.com/content/pdf/10.1007/3-540-61474-5_95.pdf

Reference9 articles.

1. A. Aziz, S. Tasiran, and R. K. Brayton. BDD Variable Ordering for Interacting Finite State Machines. In Proc. of the Design Automation Conf., pages 283–288, San Diago, CA, June 1994.

2. R. K. Brayton, G. D. Hachtel, A. Sangiovanni-Vincentelli, F. Somenzi, A. Aziz, S. T. Cheng, S. Edwards, S. Khatri, Y. Kukimoto, A. Pardo, S. Qadeer, R. K. Ranjan, S. Sarwary, T. R. Shiple, G. Swamy, and T. Villa. VIS: A System for Verification and Synthesis. Technical Report UCB/ERL M95, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, Dec. 1995.

3. S. T. Cheng. Compiling Verilog into Automata. Technical Report UCB/ERL M94/37, Electronics Research Lab, Univ. of California, Berkeley, CA 94720, May 1994.

4. E. M. Clarke, O. Grumberg, K. L. McMillan, and X. Zhao. Efficient generation of counterexamples and witnesses in symbolic model checking. In Proc. 32nd Design Automat. Conf., pages 427–432, June 1995.

5. S. Edwards. The Ext System, 1995. http://www.eecs.berkeley.edu/r~sedwards/ext.

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