Author:
Childers Bruce R.,Nakra Tarun
Publisher
Springer Berlin Heidelberg
Reference24 articles.
1. Bahar R. I., Albera G. and Manne S., “Power and performance trade-offs using various Caching Strategies”, Int’l. Symp. on Low-Power Electronics and Design, pp. 64–69, Monterey, CA, August 1998.
2. Bellas N., Hajj I., and Polychronopoulos, “Architectural and compiler support for energy reduction in the memory hierarchy of high performance microprocessors”, Int’l. Symp. on Low-Power Electronics and Design, pp. 70–75, Monterey, CA, August 1998.
3. Bunda J., Fussell D., Athas W. C., Jenevein R., “16-bit vs. 32-bit instructions for pipelined microprocessors”, ACM/IEEE Int’l. Symp. on Computer Architecture, pp. 237–246, San Diego, CA, May 1993.
4. Burger D. and Austin T. M., “The SimpleScalar tool set, version 2.0”, Technical Report #1342, Computer Science Department, University of Wisconsin-Madison, June 1997.
5. Chandrakasan A. and Brodersen R., Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. More is less;Proceedings of the 48th International Symposium on Microarchitecture;2015-12-05