Power and performance tradeoffs using various caching strategies

Author:

Bahar R. Iris,Albera Gianluca,Manne Srilatha

Publisher

ACM Press

Cited by 25 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A high level implementation and performance evaluation of level-I asynchronous cache on FPGA;Journal of King Saud University - Computer and Information Sciences;2017-07

2. An optimizing pipeline stall reduction algorithm for power and performance on multi-core CPUs;Human-centric Computing and Information Sciences;2015-01-29

3. Real-Time Power Management for Embedded M2M Using Intelligent Learning Methods;ACM Transactions on Embedded Computing Systems;2014-12-15

4. Computer-Aided Design for Energy Optimization in the Memory Architecture of Embedded Systems;Chapman & Hall/CRC Computer & Information Science Series;2011-11-16

5. Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems;Journal of Parallel and Distributed Computing;2010-10

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