System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip

Author:

Bona Andrea,Zaccaria Vittorio,Zafalon Roberto

Publisher

Kluwer Academic Publishers

Reference20 articles.

1. J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks: an Engineering Approach”, IEEE Computer Society Press, 1997.

2. K. Lahiri, S. Dey et al.,“Efficient Exploration of the SOC Communication Architecture Design Space”, Proc. of ICCAD-2000, Nov. 2000, S.Jose’, USA.

3. W. Dally, B. Toles, “Route Packets, not Wires: On-Chip Interconnection Network”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.

4. A. Sangiovanni Vincentelli, J. Rabaey, K. Keutzer et al., “Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.

5. F. Karim, A. Nguyen et al., “On Chip Communication Architecture for OC-768 Network Processors”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.

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