1. David A. Paterson, John L. Henessy – “Computer architecture. a quantitative approach”, Morgan Kaufmann Publishers, Inc. 1990-1996.
2. Ovidiu Novac, Gordan M, Novac M., Data loss rate versus mean time to failure in memory hierarchies. Advances in Systems, Computing Sciences and Software Engineering, Proceedings of the CISSE’05, Springer, pp. 305-307, University of Bridgeport, USA, 2005.
3. Ovidiu Novac, Vladutiu M, St. Vari Kakas, Novac M., Gordan M., A Comparative Study Regarding a Memory Hierarchy with the CDLR SPEC 2000 Simulator, Innovations and Information Sciences and Engineering,Proceedings of the CISSE’06, University of Bridgeport, Springer, pp. 369-372, USA, 2006.
4. Ooi, Y., M. Kashimura, H. Takeuchi, and E. Kawamura, Fault-tolerant architecture in a cache memory control LSI, IEEE J. of Solid-State Circuits, Vol. 27, No. 4, pp. 507-514, April 1992.
5. Philip P. Shirvani and Edward J. McCluskey, “PADded cache: a new fault-tolerance technique for cache memories”, Computer Systems Laboratory, Technical Report No. 00-802, Stanford University, Stanford, California, December 2000.