Conclusions
Author:
Publisher
Springer Netherlands
Link
http://link.springer.com/content/pdf/10.1007/978-90-481-3443-4_8.pdf
Reference8 articles.
1. Robertson I et al. (Nov 2005) Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. In: Proceedings of International Test Conference, pp 1–8
2. Provost B et al. (Oct 2004) PAC IO loopback design for high speed /spl mu/processor IO test. In: Proceedings of International Test Conference, pp 23–30
3. Casper B et al. (Feb 2006) A 20 Gb/s forwarded clock transceiver in 90 nm CMOS. In: Proceedings of International Solid-State Circuits Conference, pp 263–272
4. Kromer C et al. (Dec 2006) A 25-Gb/s CDR in 90-nm CMOS for high-density interconnects. IEEE J Solid State Circuit 41(12):2921–2929
5. Hidaka Y et al. (Feb 2007) A 4-Channel 3.1/10.3 Gb/s transceiver macro with a pattern-tolerant adaptive equalizer. In: Proceedings of Solid-State Circuits Conference, pp 442–445
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