1. Y. Fan, Y. Cai and Z. Zilic, "A High Accuracy, High Throughput Jitter Test Solution on ATE for 3 Gbps and 6 Gbps Serial-ATA," Proceedings of IEEE International Test Conference, Oct. 2007
2. T.J. Yamaguchi, M. Soma, M. Ishida, H. Musha, and L. Malarsie, "A New Method for Testing Jitter Tolerance of SerDes Devices Using Sinusoidal Jitter," Proceedings of IEEE International Test Conference, 2002
3. M. Li and J. B. Wilstrup, “On the Accuracy of Jitter Separation from Bit Error Rate Function,” Proceedings of IEEE International Test Conference, 2002, p710-716
4. H. Werkmann, "Enabling the PCI Express Ramp - ATE Based Testing of PCI Express Architecture," Euro DesignCon 2004 Also available at www.verigy.com
5. P. R. Trischitta and E. L. Varma, Jitter in Digital Transmission Systems, Artech House, 1989