Mobility effects due to doping, temperature and interface traps in gate-all-around FinFETs
Author:
Publisher
Springer Science and Business Media LLC
Link
https://link.springer.com/content/pdf/10.1007/s00542-024-05637-8.pdf
Reference27 articles.
1. Clarke P (2006) KAIST claims record size 3-nm FinFETs, March14, 2006. www.eetimes.com/document.asp?doc_id=1160025
2. Das D, Pandey CK (2023) Interfacial trap charge and self-heating effect based reliability analysis of a Dual-Drain Vertical Tunnel FET. Microelectron Reliab 146:115024. https://doi.org/10.1016/j.microrel.2023.115024
3. Das RR, Maity S, Chowdhury A, Chakraborty A, Mitra SK (2022) Effect of positive/negative interface trap charges on the performance of Multi Fin FinFET (M-FinFET). SILICON 14(14):8557–8566. https://doi.org/10.1007/s12633-022-01669-9
4. Das PS, Deb D, Goswami R, Sharma S, Saha R, Choudhury H (2023) A dual core S/D source/drain GAA FinFET. Tecnología Marcha J 36(6):5–11. https://doi.org/10.18845/tm.v36i6.6748
5. Das PS, Deb D, Goswami R, Sharma S, Saha R (2024) Fin core dimensionality and corner effect in dual core gate-all-around FinFET. Microelectron J 143:105985. https://doi.org/10.1016/j.mejo.2023.105985
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