Effect of Positive/Negative Interface Trap Charges on the Performance of Multi Fin FinFET (M-FinFET)
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01669-9.pdf
Reference42 articles.
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3. Manoj CR, Rao R (2007) Impact of high-k gate dielectrics on the device and circuit performance of nanoscale FinFETs. IEEE Electron Device Lett 28(4):295–297. https://doi.org/10.1109/LED.2007.892365
4. Veloso A et al. (2013) Effective work function engineering for aggressively scaled planar and multi-gate fin field-effect transistor-based devices with high-k last replacement metal gate technology. Jpn J Appl Phys 52(4 PART 2). doi: https://doi.org/10.7567/JJAP.52.04CA02
5. Transistors DC et al (1998) Gate engineering for deep-submicron CMOS Transistors. IEEE Trans. Electron Devices 45(6):1253–1262
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