Utilizing symmetry when model checking under fairness assumptions: An automata-theoretic approach

Author:

Emerson E. A.,Sistla A. P.

Publisher

Springer Berlin Heidelberg

Reference26 articles.

1. Aggarwal S., Kurshan R. P., Sabnani K. K., “A Calculus for Protocol Specification and Validation”, in Protocol Specification, Testing and Verification III, H. Ruden, C. West (ed's), North-Holland 1983, 19–34.

2. Bouajjani, A., Fernandez, J, Halbwichs, N., Raymond, P., and Ratel, C., Minimal State Graph Generation, Science of Computer Programming, 1992.

3. Clarke, E. M., and Emerson, E. A., Design and Verification of Synchronization Skeletons using Branching Time Temporal Logic, Logics of Programs Workshop 1981, Springer LNCS no. 131.

4. Clarke, E. M., Emerson, E. A., and Sistla, A. P., Automatic Verification of Finite State Concurrent Programs using Temporal Logic: A Practical Approach, ACM TOPLAS, April 1986

5. Clarke, E. M., Filkorn, T., Jha, S. Exploiting Symmetry in Temporal Logic Model Checking, 5th International Conference on Computer Aided Verification, Crete, Greece, June 1993.

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