Using formal verification/analysis methods on the critical path in system design: A case study

Author:

Eiríksson Ásgeir Th.,McMillan Ken L.

Publisher

Springer Berlin Heidelberg

Reference19 articles.

1. S. V. Adve, “Designing Memory Consistency Models For Shared-Memory Multiprocessors”, Ph.D. Thesis, U of Wisconsin-Madison, 1993.

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3. R. E. Bryant, D. L. Beatty, and C. J. Seger, “Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation”, Proc. 28th ACM/IEEE Design Automation Conf., 1991

4. E. M. Clarke, O. Grumberg, H. Hirashi, S. Jha, D.E. Long, K.L. McMillan, and L. A. Ness, “Verification of the Futurebus+ cache coherence protocol”, Proc. 11th Intl. Symp. on Computer. Hardware Description. Lang. and their Application, 1993

5. W. W. Collier, “Reasoning about Parallel Architectures”, Prentice-Hall, Englewood Cliffs, New Jersey, 1992

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