Formal hardware verification by symbolic ternary trajectory evaluation
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ACM Press
Cited by 28 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Combining Symmetry Reduction with Generalized Symbolic Trajectory Evaluation;The Computer Journal;2013-01-17
2. Symbolic execution of Reo circuits using constraint automata;Science of Computer Programming;2012-07
3. Efficient Microprocessor Verification using Antecedent Conditioned Slicing;20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07);2007
4. Symbolic Simulation, Model Checking and Abstraction with Partially Ordered Boolean Functional Vectors;Computer Aided Verification;2004
5. Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems;Design Automation for Embedded Systems;2003-06
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