Insight of surface treatments for CMOS compatibility of InAs nanowires-Reference-Cited by-同舟云学术

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Insight of surface treatments for CMOS compatibility of InAs nanowires

Published:2018-12-13 Issue:3 Volume:12 Page:581-586
ISSN:1998-0124
Container-title:Nano Research
language:en
Short-container-title:Nano Res.

Author:

Dhungana Daya S.,Hemeryck Anne,Sartori Nicolo,Fazzini Pier-Francesco,Cristiano Filadelfo,Plissard Sébastien R.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,General Materials Science,Condensed Matter Physics,Atomic and Molecular Physics, and Optics

Link

http://link.springer.com/article/10.1007/s12274-018-2257-8/fulltext.html

Reference49 articles.

1. Tomioka, K.; Yoshimura, M.; Fukui, T. Sub 60 mV/decade switch using an InAs nanowire-Si heterojunction and turn-on voltage shift with a pulsed doping technique. Nano Lett. 2013, 13, 5822–5826.

2. Kanungo, P. D.; Schmid, H.; Björk, M. T.; Gignac, L. M.; Breslin, C.; Bruley, J.; Bessire, C. D.; Riel, H. Selective area growth of III-V nanowires and their heterostructures on silicon in a nanotube template: Towards monolithic integration of nano-devices. Nanotechnology 2013, 24, 225304.

3. Lee, K. H.; Wang, Y.; Wang, B.; Zhang, L.; Sasangka, W. A.; Goh, S. C.; Bao, S. Y.; Lee, K. E.; Fitzgerald, E. A.; Tan, C. S. Monolithic integration of Si-CMOS and III-V-on-Si through direct wafer bonding process. IEEE J. Electron Devices Soc. 2017, 6, 571–578.

4. Thelander, C.; Agarwal, P.; Brongersma, S.; Eymery, J.; Feiner, L. F.; Forchel, A.; Scheffler, M.; Riess, W.; Ohlsson, B. J.; Gösele, U. et al. Nanowire-based one-dimensional electronics. Mater. Today 2006, 9, 28–35.

5. Renard, V. T.; Jublot, M.; Gergaud, P.; Cherns, P.; Rouchon, D.; Chabli, A.; Jousseaume, V. Catalyst preparation for CMOS-compatible silicon nanowire synthesis. Nat. Nanotechnol. 2009, 4, 654–657.

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