1. Ma, T. P. Making silicon nitride film a viable gate dielectric. IEEE Trans. Electron Dev. 1998, 45, 680–690.
2. Choi, Y. K.; Asano, K.; Lindert, N.; Subramanian, V.; King, T. J.; Bokor, J.; Hu, C. M. Ultrathin-body SOI MOSFET for deep-sub-tenth micron era. IEEE Electron Dev. Lett. 2000, 21, 254–255.
3. Chauhan, Y. S.; Lu, D. D.; Vanugopalan, S.; Khandelwal, S.; Duarte, J. P.; Paydavosi, N.; Niknejad, A.; Hu, C. M. FinFET Modeling for IC Simulation and Design Using the BSIM-CMG Standard; Academic Press: London, 2015.
4. Qi, S. C.; Cunha, J.; Guo, T. L.; Chen, P. Q.; Zaccaria, R. P.; Dai, M. Bottom-gate approach for all basic logic gates implementation by a single-type IGZO-based MOS transistor with reduced footprint. Adv. Sci. 2020, 7, 1901224.
5. Huang, Q. H. International technology roadmap for semiconductors (2013 Edition). China Integrated Circuit 2014, 23, 25–45.