Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration-Reference-Cited by-同舟云学术

Development of a general purpose verification environment for high-level-synthesis image processing hardware with support for dynamic partial reconfiguration

Published:2022-07-08 Issue:3 Volume:27 Page:554-560
ISSN:1433-5298
Container-title:Artificial Life and Robotics
language:en
Short-container-title:Artif Life Robotics

Author:

Shojima Atsushi,Yamawaki Akira

Publisher

Springer Science and Business Media LLC

Subject

Artificial Intelligence,General Biochemistry, Genetics and Molecular Biology

Link

https://link.springer.com/content/pdf/10.1007/s10015-022-00772-9.pdf

Reference11 articles.

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3. Mora-Gutiérrez JM, Jiménez-Fernández CJ, Valencia-Barrero M (2017) Multiradix trivium implementations for low-power IoT hardware. IEEE Trans Very Large Scale Integr VLSI Syst 25(12):3401–3405

4. Siracusa M, Rabozzi M, Del Sozzo E, Santambrogio M. D, Di Tucci L (2019) Automated Design Space Exploration and Roofline Analysis for FPGA-Based HLS Applications. In: IEEE 27th Annual international symposium on field-programmable custom computing machines (FCCM), pp 314–314

5. Prost-Boucle A, Muller O, Rousseau F (2013) A fast and autonomous HLS methodology for hardware accelerator generation under resource constraints. In: 2013 Euromicro Conference on Digital System Design, pp 201–208

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