Hardware Design of Low-Power High-Throughput Sorting Unit

Author:

Lin Shih-Hsiang,Chen Pei-Yin,Lin Yu-Ning

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Computational Theory and Mathematics,Hardware and Architecture,Theoretical Computer Science,Software

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Edge-sorter: A hardware sorting engine for area & power constrained edge computing devices;Microprocessors and Microsystems;2024-03

2. A Low-Cost Pipelined Architecture Based on a Hybrid Sorting Algorithm;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

3. Low Power Multidimensional Sorters using Clock Gating and Index Sorting;2023 IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT);2023-07-14

4. Power Efficient Image Processing with TMR Tunable Hybrid Approximate Adders;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02

5. k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-05

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