Modeling and analysis of gate-induced drain leakage current in negative capacitance junctionless FinFET
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Modeling and Simulation,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s10825-022-01930-9.pdf
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3. Gupta, S., Steiner, M., Aziz, A., Narayanan, V., Datta, S., Gupta, S.K.: Device-circuit analysis of ferroelectric FETs for low-power logic. IEEE Trans. Electron Dev. 64(8), 3092–3100 (2017). https://doi.org/10.1109/ted.2017.2717929
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