1. J. Q. Lu, 3-D hyperintegration and packaging technologies for micro-nano systems, Proceedings of the IEEE, 97 (1) (2009) 18–30.
2. Q. Chen, Y. Suzuki, G. Kumar, V. Sundaram and R. R. Tummala, Modeling, fabrication, and characterization of low-cost and high-performance polycrystalline panel-based silicon interposer with through vias and redistribution layers, IEEE Transactions on Components, Packaging and Manufacturing Technology, 4 (12) (2014) 2035–2041.
3. B. Swinnen, W. Ruythooren, P. De Moor, L. Bogaerts, L. Carbonell, K. De Munck, B. Eyckens, S. Stoukatch, D. S. Tezcan, Z. Tokei, J. Vaes, J. Van Aelst and E. Beyne, 3D integration by Cu-Cu thermo-compression bonding of extremely thinned bulk Si die containing 10 μm pitch through-Si vias, 2006 International Electron Devices Meeting, San Francisco, CA, USA (2006) 1–4.
4. J. H. Lau, Through-silicon Vias for 3D Integration, McGraw-Hill Education, USA (2013).
5. Y. C. Tan, C. M. Tan, X. W. Zhang, T. C. Chai and D. Q. Yu, Electromigration performance of Through Silicon Via (TSV)—A modeling approach, Microelectronics Reliability, 50 (9–11) (2010) 1336–1340.