Author:
Blad Anton,Gustafsson Oscar
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Reference22 articles.
1. H. Aboushady, Y. Dumonteix, M.-M. Louerat, H. Mehrez, Efficient polyphase decomposition of comb decimation filters in Σ Δ analog-to-digital converters. IEEE Trans. Circuits Syst. II 48(10), 898–903 (2001)
2. T. Achterberg, Constraint Integer Programming. Ph.D. dissertation, Technische Universität Berlin (2007). http://opus.kobv.de/tuberlin/volltexte/2007/1611/
3. A. Berkeman, V. Öwall, M. Torkelson, A low logic depth complex multiplier using distributed arithmetic. IEEE J. Solid-State Circuits 35(4), 656–659 (2000)
4. K. Bickerstaff, M. Schulte, E.E. Swartzlander Jr., Parallel reduced area multipliers. VLSI Signal Process. 9(3), 181–191 (1995)
5. A. Blad, O. Gustafsson, Bit-level optimized high-speed architectures for decimation filter applications, in Proc. IEEE Int. Symp. Circuits Syst., 2008
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