A low logic depth complex multiplier using distributed arithmetic-Reference-Cited by-同舟云学术

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A low logic depth complex multiplier using distributed arithmetic

Published:2000-04 Issue:4 Volume:35 Page:656-659
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Berkeman A.,Owall V.,Torkelson M.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/18159/00839928.pdf?arnumber=839928

Cited by 8 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Structure and Principles of Operation of a Quaternion VLSI Multiplier;Applied Sciences;2024-09-10

2. An Efficient Implementation Approach to FFT Processor for Spectral Analysis;IEEE Transactions on Instrumentation and Measurement;2023

3. Weighted Partitioning for Fast Multiplierless Multiple-Constant Convolution Circuit;IEEE Transactions on Circuits and Systems II: Express Briefs;2017-01

4. Hardware architecture for an anti-traffic noise system;Microelectronics Journal;2015-05

5. Distributed Arithmetic based Split-Radix FFT;Journal of Signal Processing Systems;2013-06-22

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