Spur Reduction Circuit for Fractional-N PLLs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-021-01900-9.pdf
Reference16 articles.
1. D. Biswas, T.K. Bhattacharyya, A model of spurs for Delta-Sigma fractional PLLs, in Proceedings: 32nd International Conference on VLSI Design, VLSID 2019—Held Concurrently with 18th International Conference on Embedded Systems, ES 2019. IEEE, pp 512–513 (2019)
2. D. Biswas, T.K. Bhattacharyya, Causes of PLL spurs and their modeling. Analog Integr. Circuits Signal Process. 100, 639–652 (2019)
3. D. Biswas, T.K. Bhattacharyya, Spur reduction architecture for multiphase fractional PLLs. IET Circuits Devices Syst. 13, 1169–1180 (2019)
4. D. Biswas, G.S. Javed, K.S.S. Reddy, 5-GHz integer-N PLL with spur reduction sampler. Electron. Lett. 55, 1217–1220 (2019)
5. Y.-W. Chen, Y.-H. Yu, Y.-J.E. Chen, A 0.18-$$\mu $$m CMOS dual-band frequency synthesizer with spur reduction calibration. IEEE Microw. Wirel. Compon. Lett. 23, 551–553 (2013)
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-Phase and 5-GHz PLL with a Subfeedback Loop Technique;Circuits, Systems, and Signal Processing;2022-10-17
1.学者识别学者识别
2.学术分析学术分析
3.人才评估人才评估
"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370
www.globalauthorid.com
TOP
Copyright © 2019-2024 北京同舟云网络信息技术有限公司 京公网安备11010802033243号 京ICP备18003416号-3