Dynamic Threshold Sleep Transistor Technique for High Speed and Low Leakage in CMOS Circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
http://link.springer.com/article/10.1007/s00034-016-0442-0/fulltext.html
Reference24 articles.
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3. A.P. Chandrakasan, Low-power CMOS digital design. IEEE J. Solid State Circuit 27, 473–484 (1992)
4. K. Chopra, S.B.K. Vrudhula, Implicit pseudo Boolean enumeration algorithms for input vector control, inProceedings of IEEE-ACM Design Automation Conference, pp. 767–772 (2004)
5. P. Corsonello, M. Lanuzza, S. Perri, Gate-level body biasing technique for high speed sub-threshold CMOS logic gates. Int. J. Circuit Theory Appl. 42, 65–70 (2014)
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