Implementation and Performance Analysis of Low Power 1 GHz 4-Bit Flash ADC Using III–V Tunnel-FET

Author:

Maurya AshishORCID,Rahi Pankaj,Koley Kalyan,Kumar Jitendra

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Reference25 articles.

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2. A. Baschirotto, V. Chironi, G. Cocciolo, S. D’Amico, M. De Matteis, P. Delizia, Low power analog design in scaled technologies. Proc. Topical Workshop Electron. Particle Phys. 103–110. (2009)

3. R. Bijesh et al., Demonstration of In 0.9Ga0.1As/GaAs0.18Sb0.82 near broken-gap tunnel FET with ION=740 µA/µm, GM=70 µS/µm and gigahertz switching performance at VDS=0.5V. Proc. IEDM. 28.2.1–28.2.4 (2013)

4. Y. Chen, K. Mouthaan, B.-L. Ooi, Performance enhancement of colpitts oscillators by parasitic cancellation. IEEE Trans. Circuits Syst. II. 55, 1114–1118 (2008)

5. C.-Y. Chen, J. Wu, J.-J. Hung, T. Li, W. Liu, W.-T. Shih, A 12-bit 3 GS/s pipeline ADC with 0.4 mm2 and 500 mW in 40 nm digital CMOS. IEEE J. Solid State Circuits. 47, 1013–1021 (2012)

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