High Energy Efficiency and Linearity Switching Scheme Without Reset Energy for SAR ADC
Author:
Funder
National Natural Science Foundation of China
Publisher
Springer Science and Business Media LLC
Subject
Applied Mathematics,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s00034-022-02038-y.pdf
Reference26 articles.
1. S.U. Baek, K.Y. Lee, M. Lee, Energy-efficient switching scheme for SAR ADC using zero-energy dual capacitor switching. Analog Integr. Circ. Signal Process. 94(2), 317–322 (2018)
2. L Chen, A Sanyal, J Ma et al. (2016) Comparator common-mode variation effects analysis and its application in SAR ADCs. In: IEEE International symposium on circuits and systems (ISCAS), Montreal, pp. 2014–2017
3. T. Chen, J. Cai, X. Li et al., High-efficient two-step switching scheme for SAR ADC with dual-capacitive arrays and four-input comparator. Analog Integr. Circ. Signal Process. 101, 363–373 (2019)
4. A.R. Ghasemi, M. Saberi, R. Lotfi, A low-power capacitor switching scheme with low common-mode voltage variation for successive approximation ADC. Microelectron. J. 61, 15–20 (2017)
5. S. Hsieh, C. Hsieh, 0.4-V 13-bit 270-kS/s SAR-ISDM ADC with Opamp-Less Time-Domain integrator. IEEE J. Solid-State Circuits 54(6), 1648–1656 (2019)
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2. A 10-bit 33.3-kS/s 3.2-fJ/conversion-step single-ended counter-type SAR ADC with dual 5-bit CDAC arrays and counters in 65-nm CMOS;AEU - International Journal of Electronics and Communications;2024-02
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