Digital System Design Using Standard NeuMOS Cells Applied in ADAS-Reference-Cited by-同舟云学术

Digital System Design Using Standard NeuMOS Cells Applied in ADAS

Published:2020-01-16 Issue:7 Volume:39 Page:3574-3594
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Medina-Santiago A.,Molina Patricia E. Vera,Barranca Mario Alfredo Reyes,Hérnandez J. A. Zepeda

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s00034-019-01325-5.pdf

Reference16 articles.

1. E.A. Cortés-Barrón, M.A. Reyes-Barranca, L.M. Flores-Nava, A. Medina-Santiago, 4-bit arithmetic logic unit (alu) based on neuron mos transistors, in 2012 9th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) (Sept 2012), p. 1–6

2. S. Dominguez-Sánchez, M.A. Reyes-Barranca, S. Abarca-Jiménez, S. Mendoza-Acevedo, A prototype design for an accelerometer using a multiple floating-gate mosfet as a transducer, in 2014 11th International Conference on Electrical Engineering, Computing Science and Automatic Control (CCE) (Sept 2014), p. 1–6

3. E. Garcia, M.A. Reyes-Barranca, V. Rincón, J. Dominguez, Comprobación de funciones lógico binarias de compuertas xor y xnor usando dispositivos de compuerta flotante, in Conferencia de Ingeniería Eléctrica, México, D.F. (September 2003)

4. R.Z. Kabai, in Applied Artificial Intelligence for Assisted and Autonomous Driving. Presentation, Continental (2018), p. 1–20

5. A. Medina-Santiago, M.A. Reyes-Barranca, I. Algredo-Badillo, A.M. Cruz, K.A.R. Gutiérrez, A.E. Cortés-Barrán, Reconfigurable arithmetic logic unit designed with threshold logic gates. IET Circuits Devices Syst. 13(9), 21–30 (2019)