Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms-Reference-Cited by-同舟云学术

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Exploring and optimizing partitioning of large designs for multi-FPGA based prototyping platforms

Published:2020-07-21 Issue:11 Volume:102 Page:2361-2383
ISSN:0010-485X
Container-title:Computing
language:en
Short-container-title:Computing

Author:

Farooq Umer^ORCID,Alzahrani Bander A.

Publisher

Springer Science and Business Media LLC

Subject

Computational Mathematics,Computational Theory and Mathematics,Computer Science Applications,Numerical Analysis,Theoretical Computer Science,Software

Link

https://link.springer.com/content/pdf/10.1007/s00607-020-00834-5.pdf

Reference44 articles.

1. Santarini M (2005) Asic prototyping: make versus buy. EDN 11

2. Sigenics: Custom Asic calculator (2017). http://www.sigenics.com/page/custom-asic-cost-calculator

3. AMD (2007). http://techreport.com/news/13721/chip-problem-limits-supply-of-quad-core-opterons

4. Pentium (1994). https://en.wikipedia.org/wiki/pentium_fdiv_bug

5. Graphics M (2017). https://www.mentor.com/products/fv/modelsim/

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1. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks;The Journal of Supercomputing;2024-06-23

2. SPARK: A Scalable Partitioning and Routing Framework for Multi-FPGA Systems;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05

3. Towards Machine Learning-Based FPGA Backend Flow: Challenges and Opportunities;Electronics;2023-02-13

4. Prototyping using multi-FPGA platform: A novel and complete flow;Microprocessors and Microsystems;2023-02

5. Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning;Electronics;2022-07-18

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