A priority-based polling scheduling algorithm for arbitration policy in Network on Chip

Author:

Bao Liyong,Zhao Dongfeng,Zhao Yifan

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference17 articles.

1. Shashi Kumar, Axel Jantsch, Juha-Pekka Soininen, et al. A network on chip architecture and design methodology. Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSL’02), Pittsburgh, USA, April 25, 2002, 105–112.

2. Sudeep Pasricha and Nikil Dutt. On-Chip Communication Architectures: System on Chip Interconnect (System on Silicon). Burlington, USA, Morgan Kaufmann, 2008, 185–186.

3. W. Wolf. The future of multiprocessor systems on chips. Proceedings of the 41st Design Automation Conference, San Diego, USA, 2004, 681–685.

4. A. A. Jerrya and W. Wolf. Multiprocessor Sytem on Chip. San Francisco, USA, Morgan Kaufmann, 2005, 46–49.

5. L Benini, D Bertozzi, A Bogliolo, et al. MPARM: Exploring the multiprocessor SoC design space with System C. Journal of VLSI Signal Processing, 41 (2005)2, 169–182.

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