Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering-Reference-Cited by-同舟云学术

Large-Area Automated Layout Extraction Methodology for Full-IC Reverse Engineering

Published:2018-10-31 Issue:4 Volume:2 Page:322-332
ISSN:2509-3428
Container-title:Journal of Hardware and Systems Security
language:en
Short-container-title:J Hardw Syst Secur

Author:

Quijada Raul,Dura Roger,Pallares Jofre^ORCID,Formatje Xavier,Hidalgo Salvador,Serra-Graells Francisco

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Building and Construction

Link

http://link.springer.com/article/10.1007/s41635-018-0051-4/fulltext.html

Reference16 articles.

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3. Chen X, Han H, Xie QW, Shen LJ (2012) Correction of SEM image distortion based on non-equidistant GM(1,1) model. In: 2012 International conference on wavelet analysis and pattern recognition, pp 20–23. https://doi.org/10.1109/ICWAPR.2012.6294748

4. Dura R, Pallares J, Quijada R, Formatje X, Hidalgo S, Serra-Graells F (2017) fast and robust Topology-Based logic gate identification for automated IC reverse engineering. In: Proceedings of the ISTFA 2017, Pasadena, USA, pp 317– 332

5. Erbagci B, Erbagci C, Akkaya NEC, Mai K (2016) A secure camouflaged threshold voltage defined logic family. In: 2016 IEEE International symposium on hardware oriented security and trust (HOST), pp 229–235. https://doi.org/10.1109/HST.2016.7495587

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