Mismatch and Noise
Author:
Publisher
Springer New York
Link
http://link.springer.com/content/pdf/10.1007/978-1-4939-2751-7_10
Reference140 articles.
1. J.-B. Shyu, G. C. Temes, and F. Krummenacher, “Random error effects in matched MOS capacitors and current sources,” IEEE J. Solid-State Circuits, SC-17, 1070-1076, 1982, and SC-19 (6), 948-955, 1984.
2. K. R. Lakshmikumar, R. A. Hadaway, and M. A. Copeland, “Characterization and modeling of mismatch in MOS transistors for precision analog design,” IEEE J. Solid-State Circuits, SC-21 (6), 1057-1066, 1986.
3. A. Hastings, The Art of Analog Layout, 254-300, Prentice Hall, 2001.
4. M. J. M. Pelgrom, A. C. J., Duinmaijer, and A. P. G., Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, 24 (5), 1433-1440, 1989.
5. P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE J. Solid-State Circuits, 40 (6), 1212-1224, 2005.
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