A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits

Author:

Lakshmikanthan Preetham,Nuñez Adrian

Publisher

Springer Berlin Heidelberg

Reference14 articles.

1. Roy, K., Prasad, S.: Low-Power CMOS VLSI Circuit Design. Wiley-Interscience, New York (2000)

2. Rabaey, J., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits - A Design Perspective, 2nd edn. Prentice Hall Publishers, New Jersey (2002)

3. Pedram, M., Rabaey, J.: Power Aware Design Methodologies. Kluwer Academic Publishers, Massachusetts (2002)

4. Benini, L., Micheli, G.D., Macii, E.: Designing low-power circuits: Practical recipes. IEEE Circuits and Systems Magazine 1(1), 6–25 (January 2001)

5. Fallah, F., Pedram, M.: Standby and active leakage current control and minimization in cmos vlsi circuits. IEICE Transactions on Electronics, Special Section on Low-Power LSI and Low-Power IP E88-C(4), 509–519 (2005)

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Static and Dynamic power optimization using Leakage Feedback approach for nanoscale CMOS VLSI circuits;2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2022-02-16

2. VCLEARIT;ACM SIGARCH Computer Architecture News;2007-12

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