Funder
Division of Computer and Network Systems
College of Engineering, Tennessee Technological University
Center of Manufacturing Research, Tennessee Tech University
Publisher
Springer Science and Business Media LLC
Reference32 articles.
1. Zhang C, Li P, Sun G, Guan Y, Xiao B, Cong J. Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pp. 161–170 (2015). ACM.
2. Odetola TA, Oderhohwo O, Hasan SR. A scalable multilabel classification to deploy deep learning architectures for edge devices. arXiv preprint 2019. http://arxiv.org/abs/1911.02098.
3. Wang C, Gong L, Yu Q, Li X, Xie Y, Zhou X. DLAU: a scalable deep learning accelerator unit on FPGA. IEEE Trans Comput Aided Des Integr Circuits Syst. 2017;36(3):513–7.
4. Odetola TA, Mohammed HR, Hasan, SR. A stealthy hardware trojan exploiting the architectural vulnerability of deep learning architectures: Input interception attack (iia). arXiv preprint 2019. http://arxiv.org/abs/1911.00783.
5. Bacis M, Natale G, Del Sozzo E, Santambrogio MD. A pipelined and scalable dataflow implementation of convolutional neural networks on fpga. In: 2017 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 90–97 (2017). IEEE.
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