Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip-Reference-Cited by-同舟云学术

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Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal Network on Chip

Published:2005 Issue: Volume: Page:1-36
ISSN:1571-5671
Container-title:Philips Research
language:
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Author:

Gangwal Om Prakash,Rădulescu Andrei,Goossens Kees,González Pestana Santiago,Rijpkema Edwin

Publisher

Springer Netherlands

Link

http://link.springer.com/content/pdf/10.1007/1-4020-3454-7_1

Reference21 articles.

1. Adriahantenaina, A., Charlery, H., Greiner, A., Mortiez, L. and Zeferino, C. A., 2003, SPIN: A scalable, packet switched, on-chip micro-network, Proc. Design, Automation and Test in Europe Conference and Exhibition (DATE).

2. ARM Ltd., 2003, AMBA AXI Protocol Specification.

3. Benini, L. and De Micheli, G., 2001, Powering networks on chips, Int'l Symposium on System Synthesis (ISSS), pp. 33–38.

4. Benini, L. and De Micheli, G., 2002, Networks on chips: A new SoC paradigm, IEEE Computer 35(1), 70–80.

5. Bolotin, E., Cidon, I., Ginosar, R. and Kolodny, A., 2004, QNoC: QoS architecture and design process for network on chip, Journal of Systems Architecture 50(2–3), 105–128. Special issue on Networks on Chip.

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