Instruction-level parallel processing: History, overview, and perspective

Author:

Rau B. Ramakrishna,Fisher Joseph A.

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Information Systems,Theoretical Computer Science,Software

Reference225 articles.

1. Acosta, R.D., Kjelstrup, J., and Torng, H.C. 1986. An instruction issuing approach to enhancing performance in multiple function unit processors.IEEE Trans. Comps., C-35, 9 (Sept.): 815?828.

2. Adam, T.L., Chandy, K.M., and Dickson, J.R. 1974. A comparison of list schedules for parallel processing systems.CACM, 17, 12 (Dec.): 685?690.

3. Advanced Micro Devices. 1989.Am29000 Users Manual. Pub. no. 10620B, Advanced Micro Devices, Sunnyvale, Calif.

4. Agerwala, T. 1976. Microprogram optimization: A survey.IEEE Trans. Comps., C-25, 10 (Oct.): 962?973.

5. Agerwala, T., and Cocke, J. 1987. High performance reduced instruction set processors. Tech. rept. RC12434 (#55845), IBM Thomas J. Watson Research Center, Yorktown Heights, N.Y.

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