Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Reference27 articles.
1. Frank DJ, Dennard RH, Nowak E, Solomon PM, Taur Y, Wong H-SP (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE 89(3):259–288. https://doi.org/10.1109/5.915374
2. Kim S, Choi WY (2017) Improved compact model for double-gate tunnel field-effect transistors by the rigorous consideration of gate fringing field. Japanese Journal of Applied Physics 56(8):084301
3. Dhar S, Pattanaik M, Rajaram P (2011) Advancement in nanoscale CMOS device design en route to ultra-low-power applications. VLSI Design 2011:1–19. https://doi.org/10.1155/2011/178516
4. Singh, Shailendra, and Balwinder Raj. "Two-dimensional analytical modeling of the surface potential and drain current of a double-gate vertical t-shaped tunnel field-effect transistor." J Comput Electron (2020): 1–10
5. Khatami Y, Banerjee K (2009) Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy- Efficient Digital Circuits. IEEE Trans Electron Devices 56(11):2752–2760. https://doi.org/10.1109/TED.2009.2030831
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