Performance analysis of sub 10 nm regime source halo symmetric and asymmetric nanowire MOSFET with underlap engineering
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-01747-y.pdf
Reference33 articles.
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3. Xie Q, Lee C-J, Xu J, Wann C, Sun JY-C, Taur Y (2013) Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs. IEEE Trans Electron Devices 60(6):1814–1819. https://doi.org/10.1109/TED.2013.2255878
4. S. -Y. Wu et al., "An enhanced 16nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications," 2014 IEEE International Electron Devices Meeting, 2014, pp. 3.1.1–3.1.4, https://doi.org/10.1109/IEDM.2014.7046970.
5. Razavieh A, Zeitzoff P, Nowak EJ (2019) Challenges and Limitations of CMOS Scaling for FinFET and Beyond Architectures. IEEE Trans Nanotechnol 18:999–1004. https://doi.org/10.1109/TNANO.2019.2942456
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