Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current-Reference-Cited by-同舟云学术

Design of CNTFET based Domino Wide OR Gates using Dual Chirality for Reducing Subthreshold Leakage Current

Published:2022-01-14 Issue:14 Volume:14 Page:8695-8706
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Magraiya Vijay Kumar^ORCID,Gupta Tarun Kumar,Garg Bharat

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-021-01623-1.pdf

Reference20 articles.

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2. Patel PK, Malik MM, Gupta TK (2018) Reliable high-yield CNTFET-based 9T SRAM operating near threshold voltage region. J Comput Electron 17:774. https://doi.org/10.1007/s10825-017-1127-z

3. Ali. K, Chaudhary A R, Juanita, K. Roy, K. and De V. “Carbon Nanotube Field- Effect Transistors for High-Performance Digital Circuits-Transient Analysis, Parasitic, and Scalability” IEEE Transactions on Electron Devices 53(11)

4. Gupta TK, Khare K (2013) Lector with Footed-Diode Inverter: A Technique for Leakage Reduction in Domino Circuits. J Circuits System and Signal Processing 32:2707–2722

5. Kao JT, Chandrakasan AP (2000) Dual-threshold voltage techniques for low-power digital circuits. IEEE J Solid-State Circuits 35(7):1009–1018. https://doi.org/10.1109/4.848210

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