Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET-Reference-Cited by-同舟云学术

Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET

Published:2020-09-16 Issue:11 Volume:13 Page:3971-3980
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Talukdar Jagritee^ORCID,Rawat Gopal,Singh Kunal,Mummaneni Kavicharan

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-020-00712-x.pdf

Reference34 articles.

1. Moore GE (2006) Cramming more components onto integrated circuits. IEEE Solid-State Circuits Soc Newsl 11:33–35

2. Iwai H (2004) CMOS scaling for sub-90 nm to sub-l0 nm. Proc. of the 17th IntI. Conference on VLSI Design (VLSID04). https://doi.org/10.1109/ICVD.2004.1260899

3. Zhou X, Long W (1998) A novel hetero-material gate (HMG) MOSFET for deep submicron ULSI technology. IEEE Trans Electron Devices 45:2546–2548

4. Sandow C, Mantl S (2011) Modeling, Fabrication and Characterization of Silicon Tunnel Field-Effect Transistors. PhD Thesis Report, RWTH Aachen, Germany. http://darwin.bth.rwth-aachen.de/opus3/volltexte/2011/3453/pdf/3453.pdf

5. Haron N Z, Hamdioui S (2008) Why is CMOS scaling coming to an END? 3rd International Design and Test Workshop. https://doi.org/10.1109/IDT.2008.4802475

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Noise behavior in GaAs0.2Sb0.8/GaSb heterojunction Source-All-Around vertical Tunnel FET: A comprehensive study;Materials Science and Engineering: B;2024-09

2. Investigation of Analog/RF behaviour of Asymmetrical Gate Tunnel FET at Cryogenic temperatures;Silicon;2024-06-05

3. Analysis of noise behavior and reliability of pocket doped negative capacitance FET under the impact of trap charges and temperature;Microelectronics Reliability;2024-01

4. Electrical Noise Analysis of Polarity Gate JLTFET;2023 9th International Conference on Signal Processing and Communication (ICSC);2023-12-21

5. Impact of Deep Cryogenic Temperatures on High-k Stacked Dual Gate Junctionless MOSFET Performance: Analog and RF analysis;Silicon;2023-10-11