A Comprehensive Review on the Single Gate, Double Gate, Tri-Gate, and Heterojunction Tunnel FET for Future Generation Devices
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-02189-2.pdf
Reference51 articles.
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2. Lu B et al (2022) A compact model for nanowire tunneling-FETs. IEEE Trans Electron Devices 69:419–426. https://doi.org/10.1109/TED.2021.3123933
3. Das D, Chakraborty U (2020) A study on dual dielectric pocket Heterojunction SOI tunnel FET performance and flicker noise analysis in presence of Interface traps. Silicon 13:787–798. https://doi.org/10.1007/s12633-020-00488-0
4. Ritam D, Subash TD, Paitya N (2020) InAs/Si hetero-junction channel to enhance the performance of DG-TFET with GrapheneNanoribbon: an analytical model. Silicon 13:1453–1459. https://doi.org/10.1007/s12633-020-00546-78
5. Ahish S, Sharma D, Kumar YBN, Vasantha MH (2016) Performance enhancement of novel InAs/Si hetero double-gate tunnel FET using Gaussian doping. IEEE Trans Electron Devices 63:288–295. https://doi.org/10.1109/TED.2015.2503141
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