Performance Analysis of III-V Hetero/Homojunction TFETs: an Analog Circuit Design Perspective-Reference-Cited by-同舟云学术

Performance Analysis of III-V Hetero/Homojunction TFETs: an Analog Circuit Design Perspective

Published:2022-06-06 Issue:18 Volume:14 Page:12525-12539
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Yadav Atul Kumar,Panwar Sourabh^ORCID,Srivastava Shobhit,Acharya Abhishek

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-022-01889-z.pdf

Reference27 articles.

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2. Liu H, Datta S, Narayanan V (2013) Steep switching tunnel FET: A promise to extend the energy-efficient roadmap for post-CMOS digital and analog/RF applications. International Symposium on Low Power Electronics and Design (ISLPED), pp 145–150. https://doi.org/10.1109/ISLPED.2013.6629285

3. Liu J, Clavel MB, Hudait MK (2019) TBAL: tunnel FET-based adiabatic logic for energy-efficient, ultra-low voltage IoT applications. IEEE J Electron Devices Soc 7:210–218. https://doi.org/10.1109/JEDS.2019.2891204

4. Zeitzoff PM (2005) MOSFET scaling trends, challenges, and key associated metrology issues through the end of the roadmap. AIP conference proceedings

5. Bol D, Ambroise R, Flandre D, Legat J (2009) Interests and limitations of technology scaling for subthreshold logic. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(10):1508–1519. https://doi.org/10.1109/TVLSI.2008.2005413

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