An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications-Reference-Cited by-同舟云学术

An Improved Analog/RF and Linearity Performances with Small-Signal Parameter Extraction of Virtually Doped Recessed Source/Drain Dopingless Junctionless Transistor for Radio-Frequency Applications

Published:2020-06-17 Issue:5 Volume:13 Page:1519-1539
ISSN:1876-990X
Container-title:Silicon
language:en
Short-container-title:Silicon

Author:

Verma Prateek Kishor^ORCID,Gupta Santosh Kumar

Publisher

Springer Science and Business Media LLC

Subject

Electronic, Optical and Magnetic Materials

Link

https://link.springer.com/content/pdf/10.1007/s12633-020-00518-x.pdf

Reference30 articles.

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3. Hisamoto D (2001) FD/DG-SOI MOSFET-a viable approach to overcoming the device scaling limit. International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224). IEEE. https://doi.org/10.1109/IEDM.2001.979528

4. Pfiester JR, Sivan RD, Liaw HM, Seelbach CA, Gunderson CD (1990) A self-aligned elevated source/drain MOSFET. IEEE electron device letters 11(9):365–367. https://doi.org/10.1109/55.62957

5. Zhang Z, Zhang S, Chan M (2004) Self-align recessed source drain ultrathin body SOI MOSFET. IEEE Electron Device Letters 25(11):740–742. https://doi.org/10.1109/LED.2004.837582

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