Design and Performance Evaluation of a Novel Dual Tunneling based TFET Considering Trap Charges for Reliability Improvement
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-022-02188-3.pdf
Reference44 articles.
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2. Kim SW, Kim JM, Liu T-JK, Choi WY, Park B-G (2016) Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans Electron Devices 63(4):1774–1778
3. Seabaugh C, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110
4. Avci UE, Morris DH, Young LA (2015) Tunnel field-effect transistors: Prospects and challenges. IEEE J. Electron Devices Soc 3(3):88–95
5. Saripalli V, Mishra A, Datta S, Narayanan V (2011) An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores. Proc. 48th ACM/EDAC/IEEE Design Autom Conf (DAC). New York, pp 729–734
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1. Design and analysis of novel bilateral tunnelling based tunnel FET considering workfunction engineered metal strip for enhanced performance;Microelectronics Journal;2023-09
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