Modeling Analysis and Geometric Investigation of SOI FinFET for RF/AF Parameters
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01574-7.pdf
Reference30 articles.
1. Choi Y-K et al (May 2000) Ultrathin-Body SOI MOSFET for Deep-Sub-Tenth Micron Era. IEEE Electron Device Lett. 21(5):254–255. https://doi.org/10.1109/55.841313
2. Hisamoto D, Lee WC, Kedzierski J, Takeuchi H, Asano K, Kuo C, Hu C (2000) FinFET-a Self-Aligned Double-Gate MOSFET Scalable to 20 Nm. IEEE transactions on electron devices 47(12):2320–2325
3. Morris DH, Avci UE and Young IA., Intel Corp US Patent Application 15/992, 080, 2019.
4. Dixit A, Kottantharayil A, Collaert N, Goodwin M, Jurczak M, De Meyer K: Analysis of the Parasitic S/D Resistance in Multiple-Gate FETs, IEEE Trans. Electron Dev., vol. 52, no. 6, pp. 1132–1140 (2005). doi: 10.1109/ TED.2005.848098.
5. Hisamoto D et al (Dec. 2000) FinFET-a Self-Aligned Double-Gate MOSFET Scalable to 20 Nm. IEEE Trans Electron Devices 47(12):2320–2325. https://doi.org/10.1109/16.887014
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