Back Bias Induced Modeling of Subthreshold Characteristics of SOI Junctionless Field Effect Transistor (JLFET)
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-020-00590-3.pdf
Reference21 articles.
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3. Rassekh A, Fathipour M (2020) A single-gate SOI nanosheet Junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET. J Comput Electron 19:631–639. https://doi.org/10.1007/s10825-020-01475-9
4. Celler GK (2003) Frontiers of silicon-on-insulator. J Appl Phy 93:4955–4978
5. Gola D, Singh B, Tiwari PK (2017) A threshold voltage model of tri-gate junctionless field-effect transistors including substrate bias effects. IEEE Trans Elec Dev 64:3534–3540
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