Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware-Reference-Cited by-同舟云学术

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Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

Published:2011-03-13 Issue:3 Volume:12 Page:305-327
ISSN:1389-2576
Container-title:Genetic Programming and Evolvable Machines
language:en
Short-container-title:Genet Program Evolvable Mach

Author:

Vasicek Zdenek,Sekanina Lukas

Publisher

Springer Science and Business Media LLC

Subject

Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s10710-011-9132-7.pdf

Reference55 articles.

1. F.V. Andrade, M.C.M. Oliveira, A.O. Fernandes, C.J.N. Coelho, Sat-based equivalence checking based on circuit partitioning and special approaches for conflict clause reuse, in IEEE Design and Diagnostics of Electronic Circuits and Systems (IEEE Comp. Society, 2007), pp. 1–6

2. F.V. Andrade, L.M. Silva, A.O. Fernandes, in 26th International Conference on Computer Design, ICCD 2008. Improving SAT-based combinational equivalence checking through circuit preprocessing, 40–45 (2008)

3. Berkley Logic Synthesis and Verification Group: ABC: A System for Sequential Synthesis and verification. http://www.eecs.berkeley.edu/~alanmi/abc/

4. R.K. Brayton, G.D. Hachtel, C.T. McMullen, A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. (Kluwer, Boston, MA, USA, 1984)

5. J. Cong, K. Minkovich, Optimality study of logic synthesis for LUT-based FPGAs. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 26(2), 230–239 (2007)

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