The route to a defect tolerant LUT through artificial evolution

Author:

Djupdal Asbjoern,Haddow Pauline C.

Publisher

Springer Science and Business Media LLC

Subject

Computer Science Applications,Hardware and Architecture,Theoretical Computer Science,Software

Reference33 articles.

1. Altera. Apex redundancy. http://www.altera.com/products/devices/apex/features/apx-redundancy.html

2. C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli, A CMOS fault tolerant architecture for switch-level faults. in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 10–18, 1994

3. C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli, Static redundancy techniques for CMOS gates. in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 576–579, 1996

4. C. Bolchini, G. Buonanno, D. Sciuto, R. Stefanelli, An improved fault tolerant architecture at CMOS level. in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2737–2740, 1997

5. R.O. Canham, A.M. Tyrrell, Evolved fault tolerance in evolvable hardware. In Congress on Evolutionary Computation (CEC), pp. 1267–1271, 2002

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Robustness to Bit Inversion in Registers and Acceleration of Program Evolution in On-Board Computer;Journal of Advanced Computational Intelligence and Intelligent Informatics;2011-10-20

2. The evolution of standard cell libraries for future technology nodes;Genetic Programming and Evolvable Machines;2011-04-21

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