Using Arm’s scalable vector extension on stencil codes-Reference-Cited by-同舟云学术

Using Arm’s scalable vector extension on stencil codes

Published:2019-04-08 Issue:3 Volume:76 Page:2039-2062
ISSN:0920-8542
Container-title:The Journal of Supercomputing
language:en
Short-container-title:J Supercomput

Author:

Armejach Adrià^ORCID,Caminal Helena,Cebrian Juan M.,Langarita Rubén,González-Alberquilla Rekai,Adeniyi-Jones Chris,Valero Mateo,Casas Marc,Moretó Miquel

Funder

Horizon 2020 Framework Programme

Ministerio de Economía, Industria y Competitividad, Gobierno de España

Departament d’Universitats, Recerca i Societat de la Informació

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Information Systems,Theoretical Computer Science,Software

Link

http://link.springer.com/content/pdf/10.1007/s11227-019-02842-5.pdf

Reference34 articles.

1. Stephens N, Biles S, Boettcher M, Eapen J, Eyole M, Gabrielli G, Horsnell M, Magklis G, Martinez A, Prémillieu N, Reid A, Rico A, Walker P (2017) The ARM scalable vector extension. IEEE Micro 37(2):26–39. https://doi.org/10.1109/MM.2017.35 [Online]

2. Yoshida T (2016) Introduction of Fujitsu’s HPC processor for the post-K computer. In: Hot Chips 28 Symposium (HCS), Ser. Hot Chips’16. IEEE

3. Datta K, Murphy M, Volkov V, Williams S, Carter J, Oliker L, Patterson DA, Shalf J, Yelick KA (2008) Stencil computation optimization and auto-tuning on state-of-the-art multicore architectures. In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2008, November 15–21, 2008, Austin, Texas, USA, p. 4. https://doi.org/10.1145/1413370.1413375

4. Yount C, Tobin J, Breuer A, Duran A (2016) YASK–yet another stencil kernel: A framework for HPC stencil code-generation and tuning. In: Sixth International Workshop on Domain-Specific Languages and High-Level Frameworks for High Performance Computing, WOLFHPC@SC 2016, Salt Lake, UT, USA, November 14, 2016, pp 30–39. https://doi.org/10.1109/WOLFHPC.2016.08

5. Frigo M, Strumpen V (2005) Cache oblivious stencil computations. In: Proceedings of the 19th Annual International Conference on Supercomputing, ICS 2005, Cambridge, MA, USA, June 20–22, pp 361–366. https://doi.org/10.1145/1088149.1088197

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