Surix: Non-blocking and low insertion loss micro-ring resonator-based optical router for photonic network on chip
Author:
Publisher
Springer Science and Business Media LLC
Subject
Hardware and Architecture,Information Systems,Theoretical Computer Science,Software
Link
https://link.springer.com/content/pdf/10.1007/s11227-020-03442-4.pdf
Reference35 articles.
1. Khoroush S, Reshadi M, Khademzadeh A (2018) Application mapping in hybrid photonic networks-on-chip for reducing insertion loss. J Supercomput. https://doi.org/10.1007/s11227-018-2458-7
2. Vahidifar S, Reshadi M (2017) Loss-aware routing algorithm for photonic networks on chip. J Supercomput. https://doi.org/10.1007/s11227-017-2096-5
3. Ben Ahmed A, Ben Abdallah A (2015) Hybrid silicon-photonic network-on-chip for future generations of high-performance many-core systems. J Supercomput. https://doi.org/10.1007/s11227-015-1539-0
4. Reza A, Sarbazi-Azad H, Khademzadeh A, Shabani H, Niazmand B (2013) A loss aware scalable topology for photonic on chip interconnection networks. J Supercomput. https://doi.org/10.1007/s11227-013-1026-4
5. Hesham S, Rettkowski J, Goehringer D, Abd El Ghany MA (2017) Survey on real-time networks-on-chip. IEEE Trans Parallel Distrib Syst 28(5):1500–1517
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