Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA

Author:

Xing KeFei,Yang JianWei,Zhang ChuangSheng,He Wei

Publisher

Springer Science and Business Media LLC

Subject

General Engineering,General Materials Science

Reference21 articles.

1. Joseph J F, Austin L, Carmichael C, et al. The NSEU response of static Latch-based FPGAs. In: Proceedings of IEE Seminar on Cosmic Radiation—Single Event Effects and Avionics. London: Institution of Engineering and Technology, 2005. 4-1–4-25

2. Norton C D, Werne T A, Pingree P J, et al. An evaluation of the Xilinx Virtex-4 FPGA for on-board processing in an advanced imaging system. In: Proceedings of 2009 IEEE Aerospace Conference. Big Sky, MT, United states: IEEE Computer Society, 2009. 1–9

3. Irom F, Farmanesh F F. Frequency dependence of single-event upset in advanced commercial PowerPC microprocessors. IEEE Trans Nuclear Sci, 2004, 51: 3505–3509

4. Xing K F, Yang J, Wang Y K, et al. Study on the anti-radiation technique for Xilinx SRAM-based FPGA. Chinese J Astronaut, 2007, 28: 123–129

5. Pratt B, Caffrey M, Graham P, et al. Improving FPGA design robustness with partial TMR. In: Proceedings of 2006 IEEE International Reliability Physics Symposium. San Jose, CA: Institute of Electrical and Electronics Engineers Inc., 2006. 226–232

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