Architecture design for reliable and reconfigurable FPGA-based GNC computer for deep space exploration

Author:

Yang MengFei,Liu Bo,Gong Jian,Liu HongJin,Hu HongKai,Dong YangYang,Shi Lei,Zhao YunFu,Miao ZhiFu

Publisher

Springer Science and Business Media LLC

Subject

General Engineering,General Materials Science

Reference16 articles.

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2. Chen C, Yang M, Liu H. The design and verification of triple modular redundancy MPSOC fault-tolerant processor. Aerosp Contr Appl, 2012, 38: 45–50

3. She X, McElvain K S. Time multiplexed triple modular redundancy for single event upset mitigation. IEEE T Nucl Sci, 2009, 56: 2443–2448

4. Ebrahimi M, Miremadi S G, Asadi H, et al. Low-cost scan-chainbased technique to recover multiple errors in TMR systems. IEEE T Vlsi Syst, 2013, 21: 1454–1468

5. Yousuf S, Jacobs A, Gordon-Ross A. Partially reconfigurable system-on-chips for adaptive fault tolerance. In: Proceedings of IEEE International Conference on Field-Programmable Technology (FPT), New Delhi, India, 2011

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